TEVOS

Sr Principal Design Engineer

Cadence Design · Bengaluru, India

Engineering Principal Full-time Verified source Salary not disclosed

Posted 21 Oct 2026 (first seen by Tevos)
Last confirmed 25 Oct 2026 (last seen by Tevos)

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Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Senior Principal Engineer SI/PI:

Candidate will own and Lead HBM PHY SI/PI design. Candidate shall make technical decisions improving quality and schedule of program. Candidate would coordinate SI/PI deliverables. Candidate shall organize and conduct thorough project gate design reviews. Candidate will review HBM PHY customer Interposer and Package designs.

We’re doing work that matters. Help us solve what others can’t.

Source: Cadence Design careers page, collected by Tevos on 25 Oct 2026; verify details on the employer site. Tevos does not take applications — the Apply button opens the employer’s own page.

Apply on Cadence Design site ↗