Job description
Responsibilities will include, but are not limited to:
- Support process development activities through memory cell-based test structure solutions by actively engaging with Process Integration, Product and Die Design, Electrical Characterization, Advanced Mask Development and Design Rule teams.
- Interpret electrical DUT (Device under Test) definition and build completed TEGs (Test Element Groups) with high confidence functionality on Silicon.
- Implement novel solutions as the need arises to study the failure mechanisms and to monitor the health of silicon.
- Assist with parametric correlation and debug to ensure design accuracy.
- Verify and validate test structure documentation and related parametric information.
Minimum Qualifications for this position include:
- Bachelor of Science in Electrical or Microelectronic Engineering with 5 years of experience,
- Hands-on experience and proficiency in EDA tools such as Cadence Virtuoso Layout and Schematic Editor, and Calibre.
- Excellent circuit design, layout, schematic, and verification skills including DRC, LVS, and circuit simulation (hspice).
- Excellent knowledge of semiconductor device physics, operation, parametric testing, and Design for Manufacturability (DFM).
- Good knowledge of DRAM and NAND Memory Array design architectures, Fab processes, and failure modes
- Excellent problem-solving and strong people skills.
- A global mindset to seamlessly work across cultures and a sense of ownership to independently drive improvements on department level projects.
Preferred qualifications:
- Master of Science in Electrical or Microelectronic Engineering with 3 years of experience.
- Proficiency in Perl, Skill code, and UNIX shell scripting languages.
- Willingness to learn new skills and explore unfamiliar concepts.