TEVOS

Lead Design Engineer

Cadence Design · Pune, India

Engineering Lead Full-time Verified source Salary not disclosed

Posted 5 Aug 2026 (first seen by Tevos)
Last confirmed 25 Oct 2026 (last seen by Tevos)

Apply on Cadence Design site ↗

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

3++ Year ASIC Design / Verification experience. Required Expertise in PCIe / Storage (ONFI, XSPI, SD/eMMC) Design and Verification domain. Good debug skills and good communication skills.

We’re doing work that matters. Help us solve what others can’t.

Source: Cadence Design careers page, collected by Tevos on 25 Oct 2026; verify details on the employer site. Tevos does not take applications — the Apply button opens the employer’s own page.

Apply on Cadence Design site ↗