Job description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
- Development, automation and maintenance of EDA flows and scripts for physical implementation
- Develop TFM to optimize PPA for IP’s and Soft Controllers
- PPA characterization and optimization of flow for performance-oriented and power-oriented best-in-class IP cores in advanced process nodes, on TSMC, Intel, Samsung and Rapidus Foundries
- Manage regression infrastructure that tracks quality of the RTL/flow development as well as the PPA of the key designs.
- Digital design implementation using Cadence EDA tools - Genus, Innovus, Conformal, Litmus, Tempus, Voltus, Certus, Pegasus and other backend tools
- Candidate will be working on automation of Full chip floorplanning using latest AI tools. Involving in active AI agent based partition for Full Chip Floorplanning.
- Required skills –
- Educational Qualification: MS/MTech/BE/ BTech in Electronics from reputed institutes with 5 + years' experience
- Physical design experience in ASIC design environment
- Should have knowledge of complete ASIC Design Flow, including Synthesis, Physical Designing , Timing Analysis, Power Analysis and Formal Verification
- Should have excellent leadership, communication, analytical and problem solving skills.
- Expertise on High frequency design methodologies for complete ASIC backend flows.
- Candidate with experience in Full Chip (SoC level) floorplanning, pin assignment, global clock distribution across all subsystems is a plus point.
- Good communication skills, strong analytical problem solving skills and willingness to learn quickly.
- Solid scripting skills including Python and Tcl.
- Should be self-motivated and good team player.